VLSI - Memory Layout Associate II Job in Bangalore at UST Global

UST Global is hiring for the role of VLSI - Memory Layout Associate II!

Responsibilities of the Candidate:

• Work on layouts of key memory building blocks such as control, sense amplifiers, I/O blocks, bit cell arrays, and decoders in a compiler context.
• Perform top-level memory integration and handle DRC, LVS, density verification, and cleaning physicals across the compiler space.
• Address IR/EM-related issues in memory layouts.
• Collaborate with external customers and work effectively within cross-functional teams.

Requirements:

• Hands-on experience with 16nm, 14nm, 10nm, 7nm, or FinFET process technologies.
• Proficiency with Cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks.
• Strong understanding of ultra-deep sub-micron layout design challenges and DFM guidelines.
• Experience or strong interest in memory compilers.
• Excellent teamwork skills and ability to work with external customers.