Standard Cell Design Engineer Job in Bengaluru at Intel

Intel is hiring for the role of Standard Cell Design Engineer!

Responsibilities of the Candidate:

• Design and implementation of the combinatorial, clock, power management, and sequential circuits for Intel's newest process technologies.
• Parasitic extraction and circuit optimization for power/performance/robustness/density.
• Library characterization for timing, noise, power, and variation models (non-linear delay models; composite current source models, parametric on-chip variation models).
• Physical View (NDM, LEF, GDS, OASIS, OALIBS) generation for standard cell libraries.
• Reliability verification of standard cells covering ERC, EM, SH, and FinFet self-heating. APL characterization and modeling.
• Developing functional models behavioral Verilog, power udp Verilog, and fault models.
• Development of automation for library modeling, validation, quality checking, performance, and reliability verification.
• The library build, validation, QA, release, and support.
• Technically lead a team of engineers, debug problems, remove execution roadblocks, detailed planning of execution/releases, and work on strategic initiatives for future technologies

Requirements:

• Experience in digital circuit design, including CMOS combinatorial logic and sequential element design and layout. Good understanding of device physics and FinFet characteristics.
• Experience using industry-standard design automation tools in one or more of the areas: circuit simulation, std cell characterization, synthesis, place and route, physical design verification, and reliability verification.
• Experience in scripting (TCL, Perl, Python, ML) for design automation.
• Experience working in the Linux environment and its development tools.