SoC Power Design Engineer: Silicon Job in Bangalore at Google

Google is hiring for the role of SoC Power Design Engineer: Silicon!

Responsibilities of the Candidate:

• Work with Arch, Micro Arch, and RTL design teams on capturing power intent and convergence.
• Review the front-end low-power static checks and drive UPF and VCLP convergence and signoff.
• Support RTL and DFT teams on the UPF aspect in incorporating the Physical Design team feedback.
• Work with coss-domains like DFT, DV, and RTL in addressing any UPF/Power intent-related methodologies and challenges.

Requirements:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
• Experience with computer architecture concepts, including microarchitecture, cache hierarchy, pipelining, and memory subsystems
• Experience with physical design flows and Design Verification downstream usage
• Master's degree in Electrical Engineering or Computer Science
• Experience with low-power design techniques and methodologies
• Experience with scripting languages such as Python and Perl
• Understanding of SoC Architecture, memory hierarchy, coherency, fabric interconnect protocols, clocking, and power management