SOC Design Verification Job in Bangalore at Rivos Inc.

Rivos is hiring for the role of SOC Design Verification!

Responsibilities of the Candidates:

• Work closely with architecture and RTL designers on verifying the functionality correctness of the design
• Reviewing Architecture and Design Specifications
• Develop test plans and test environments
• Develop tests in assembly, C/C++, SystemVerilog, or vectors according to test plans
• Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered
• Develop checkers in SystemVerilog or C-base transactors to verify the design
• Write assertions and apply formal verification to the design implementing test benches, generating directed/constrained random tests
• Debugging failures, running simulations, tracking bugs
• Handling schedules and supporting multi-functional engineering effort assisting in verification flows, automation scripts, and regressions

Requirements:

• In-depth knowledge of digital logic design, CPU/SOC architecture, and microarchitecture.
• Sophisticated knowledge of SystemVerilog.
• Experienced level knowledge of C/C++.Relevant knowledge of verification methodologies and tools such as simulators, waveform viewers, build and run automation, and coverage collection.
• Basic knowledge of formal verification methodology is a plus.
• Excellent knowledge of of scripting languages such as Python, and TCL is a plus.
• Excellent skills in problem-solving, written and verbal communication, excellent organization skills, and highly self-motivated.
• Ability to work well in a team and be productive under aggressive schedules.
• PhD, Master’s Degree, or Bachelor’s Degree in a technical subject area.