SOC Clock Lead - SMTS Silicon Design Engineer Job in Bengaluru at AMD

AMD is hiring for the role of SOC Clock Lead - SMTS Silicon Design Engineer!

Responsibilities of the Candidate:

• Proficiency in clock tree synthesis (CTS) and clock network optimization using tools like Synopsys FC, ICC2.
• Strong experience in static timing analysis (STA), clock domain crossing (CDC) checks, and jitter/skew analysis.
• In-depth knowledge of clock gating, power optimization, and low-power design techniques.
• Strong scripting skills in Tcl, Perl, or Python for automation and flow enhancements
• Familiarity with advanced technology nodes (5nm and below) and their specific challenges in clock design
• Understanding of signal integrity, electromigration, and power integrity in the context of clock networks.
• Define and implement the clock architecture and distribution strategy for SoCs, optimizing for performance, area, and power requirements.
• Lead clock tree synthesis, insertion, and optimization to achieve timing closure and reduce clock skew/jitter across the SoC.
• Implement and validate clock gating techniques to minimize dynamic power consumption and enhance SoC energy efficiency
• Work with RTL, timing, power, and PD teams to resolve clock-related issues, optimize clock distribution, and ensure alignment with SoC design goals
• Create and maintain custom scripts in Perl, Python, or Tcl to automate clocking tasks, streamline workflows, and improve productivity

Requirements:

• Bachelors or Masters degree in computer engineering/Electrical Engineering