Senior Silicon Design Engineer Job in Bangalore at AMD

AMD is hiring for the role of Senior Silicon Design Engineer!

Responsibilities of the Candidate:

• Design and implement state of the art DFT architecture to meet growing industry demands for efficient test and debug capabilities.
• Generate and Insert DFT structures at the RTL and gate level and verifying correct operation of those structures from RTL to back annotated gates.
• Generate scan inserted netlists, produce ATPG patterns to achieve coverage targets and simulate them for correctness.
• Run timing analysis, review constraints and waivers, analyze violations and work with other teams to fix the design.
• Produce ATE test patterns for MBIST, Scan, Functional & analog testing and support silico ATE testing and debug.
• Participate in diagnostics and failure analysis for customer returns.
• Mentor and lead a team of junior engineers to accomplish all the above tasks within the defined project constraints.

Requirements:

• Hands on experience in Inserting Scan and generating
• ATPG vectors for Stuck-At and At-Speed Faults.
• In-depth experience in analysing and improving scan coverage
• Hands on experience in MBIST (insertion and simulation)
• Experience in Boundary Scan and P1500
• Experience in RTL based and netlist-based insertion flows
• Experience in DFT simulation with and without SDF
• Experience in Synthesis and formal verification tools
• Experience in generating TDL for ATE and working closely
• with ATE team during bring-up phase
• Good exposure to DFT tools from Mentor, Synopsys and Cadence
• Good scripting knowledge in Perl and TCL
• SSN knowledge is a plus
• C++ knowledge is a plusBachelor’s or master’s degree in computer engineering/Electrical Engineering