RTL Design Engineer Job in Bangalore at Google

Google is hiring for the role of RTL Design Engineer!

Responsibilities of the Candidate:

• Define the block-level design document (i.e., interface protocol, block diagram, transaction flow, pipelines, etc)
• Perform RTL development (i.e., coding and debugging in Verilog, SystemVerilog) function/performance simulation debugging and Lint/CDC/FV/UPF checks
• Participate in synthesis, timing/power closure, and FPGA/silicon bring-up
• Participate in test plan and coverage analysis of the block and SoC-level verification
• Communicate and work with multi-disciplined and multi-site teams

Requirements:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience
• 2 years of experience with RTL design using Verilog/System Verilog and
•  microarchitecture
• Experience with ARM-based SoCs, interconnects and ASIC methodologyMaster’s degree in Electrical Engineering or Computer Engineering
• 3 years of experience with IP design for clocking, interconnects, peripherals
• Experience with methodologies for low power estimation, timing closure, synthesis
• Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC)