Principal DFT Engineer/DFT Timing Lead Job in Bengaluru at Arm Technologies

Arm is hiring for the role of Principal DFT Engineer/DFT Timing Lead!

Responsibilities of Candidate:

• Lead DFT design and STA constraints to meet design PPA targets.
• Coordinates DFT requirements across SOC, IP and product teams.
• Architect, implement and validate innovative DFT techniques on SOCs and sub-systems.
• Insert DFT logic into SoC as well as sub-system level and validate all DFT features using industry-standard simulation tools.
• Work closely with multi-functional teams to support DFT RTL level insertion, synthesis and scan insertion, place-and-route, and static-timing-analysis and timing closure.
• Participate in ATE-targeted test patterns, validation and silicon - debugging.
• Work closely with Test and product engineering teams on silicon characterization and validation.

Requirements:

• This role is for a Principal DFT Engineer/DFT Timing Lead with proven experience in Design for Test
• Understanding of DFT timing signoff modes and constraints and familiarity with Synthesis and Static Timing Analysis
• Experience in validating and supporting DFT timing constraints in Geuns, Innovus, Fusion compiler, and PrimeTime
• Experience in Siemens DFT tool, Streaming Scan Network (SSN), Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debug, memory and scan diagnostics
• Experience coding Verilog RTL, TCL and/or Perl