Physical Design Engineer Job in Bangalore at Intel

Intel is hiring for the role of Physical Design Engineer!

Responsibilities of the Candidate: 

• Design Enablement team in India, is part of Intel Foundry, having charter to develop a methodology for advanced process nodes, providing the opportunity, to be among the first one to work on the latest technology. This role in Design
• Enablement, is for experienced Individual contributors for Physical design of digital blocks using Synthesis -Automatic Placement and Route flow, from RTL to GDS, including sign off for Timing, Reliability and Layout verification.
• Candidate is expected to develop and support solutions in a wide variety of activities related to Synthesis, Floor planning, Placement, Clock Tree Synthesis, Routing, Timing convergence, Scan, Hard Macro integration and Physical convergence. The candidate will be responsible for, constraint development, flow optimization to meet design requirements, by working with RTL developers, the CAD team and EDA vendors.
• This role requires good understanding of analysis and sign off flow for project, and candidate should be able to provide solution to team, by working with CAD team and EDA vendors. This role also requires transparent and clear communication and mindset to excel at work in collaborative environment with teams in other domains and Geos.

Requirements:

• Candidate must have 3+ years of relevant experience with Master's degree (M.Tech/MS) in Microelectronics/ Electronics Engineering or equivalent qualification from reputed institute. Candidate should have worked on block closure using industry-standard tool for SAPR flow and should have good knowledge of Floor planning, Power planning, Placement, Clock Tree Synthesis and Routing. You should be well versed with multiple optimization options for design closure and expected to provide solutions to team for complex implementation issues.
• Candidate should have good understanding of timing concepts and expected to analyze the constraint used for design and its impact on timing closure. You should have worked on Layout closure for the blocks, ensuring DRC, LVS, density and Antenna requirements are met as per specification.
• Candidate should have good knowledge of VLSI and digital electronics and understanding of semiconductor devices, circuits, timing closure of digital design.
• Understanding of fabrication and process technology will be added advantage. Any scripting language experience, like perl, TCL, or python would be plus point.
• Candidate should have good analytical, and problem-solving skill for debugging issues faced at work., proactive and transparent communication.
• Candidate should be having mindset to work in diverse and collaborative environment with teams in different domains and Geos.