- Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
- Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
- Estimate the time required to write the new feature tests and any required changes to the test environmen
- Build the directed and random verification tests
- Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
- Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
Requirements:
- Proficient in IP/Sub-System/SOC level ASIC verification
- Proficient in debugging firmware and RTL code using simulation tools
- Proficient in using UVM test benches and working in Linux and Windows environments
- Experienced with Verilog, System Verilog, C, and C++
- Processor Micro-Architecture concepts – Reset/Boot-flow/Cache Coherency/Interrupt flows knowledge