Memory Layout Design Engineer Job in Bengaluru at Google

Google is hiring for the role of Memory Layout Design Engineer!

Responsibilities of the Candidate:

• Integrate various blocks of the memory array and optimize the leaf cell layout used in memory arrays to achieve the best PPA.
• Track planning and power grid planning of memory arrays.
• Run LVS/DRC/density checks and fix EM/IR violations.
• Work with the circuit design team to improve the PPA of the memory array or std-cell.
• Collaborate with the physical design team to ensure that GDS can be integrated within the SoC.

Requirements:

• Bachelor’s degree in VLSI/Computer Engineering or equivalent practical experience.
• 2 years of experience designing and drawing layouts of high-speed/low-power memories.
• Experience with developing memory array layout (Row decoders, Write drivers, Assist circuits, Sense Amplifiers, Memory Control circuit) in 3nm (or equivalent) technology node.
• Experience with integrating various blocks of memory array and integrating memory array at SoC level.