DV Engineer Job in Hyderabad at AMD

AMD is hiring for the role of DV Engineer!

Responsibilities of the Candidate: 

• Strong knowledge in IP/SOC design methodologies.
• Sound knowledge of RTL/SOC design/integration with Verilog/system Verilog
• Mentoring juniors and enhancing their skill set
• Must have strong knowledge of AMBA AHB/AXI protocol
• Working knowledge on code coverage, functional coverage, Lint, CDC etc
• IP development and coding using standard coding guide lines knowledge
• Excellent communication skills. Must be able to participate & lead in global meetings
• Soft skills to be able to work in a cross functional international team digital and software design engineers
• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
• Estimate the time required to write the new feature tests and any required changes to the test environment
• Build the directed and random verification tests
• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues 
• Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requireme

Requirements:

• 5+ years for experience
• Proficient in IP-level ASIC verification
• Proficient in debugging firmware and RTL code using simulation tools 
• Proficient in using UVM test benches and working in Linux and Windows environments
• Experienced with Verilog, System Verilog, C, and C++  
• Graphics pipeline knowledge
• Developing UVM-based verification frameworks and test benches, processes and flows
• Automating workflows in a distributed computing environment.  
• Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
• Strong background in the C++ language, preferably on Linux with exposure to the Windows platform
• Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
• Good working knowledge of SystemC and TLM with some related experience.  
• Scripting language experience: Perl, Ruby, Makefile, shell preferred.  
• Exposure to leadership or mentorship is an asset
• Desirable assets with prior exposure to video codec systems or other multimedia solutions.