Digital Design Engineer Job in Bangalore at Analog Devices

Analog Devices Inc. is hiring for the role of Digital Design Engineer!

Responsibilities of the Candidate:

• Work closely with the architecture team to develop detailed specifications, search, and development plans.
• Design key digital blocks such as accelerators/datapath IP in Verilog/System Verilog with built-in configuration to allow power/performance/area tradeoffs.
• Develop a strong understanding of heterogeneous processor cores & subsystems (ARM / RISC-V/DSP core, and associated infrastructure such as caches, interconnect fabric, GIC, DMA, MMU, Coresight Debug & Trace, TZC, SMPU, SPU) and their integration requirements.
• Develop user guides for RTL Integration, Synthesis, Lint/CDC waivers, DFT, PnR, Programming Sequence, characterization, etc.
• Evaluate 3rd party IPs on Power/ Performance/ Area (PPA) and other key qualitative aspects such as design quality, Design For Testability, robustness of Design Verification (DV) practice, ease of integration, and make recommendations.
• Provide technical leadership and guidance to small teams of Micro-architects/RTL developers working on an SoC.
• Work closely with the verification team for vPlan reviews and for complex debugs to resolve verification failures.
• Participate in design specification, microarchitecture and verification sign-off reviews.
• Improve flows and methodologies to streamline IP development and integration.
• Build (including recruiting and interviewing) development teams.

Requirements:

• Minimum B.E./B.Tech degree in Electrical/Electronics/Computer Science.
• 2-6 years of digital logic design and hands-on RTL coding experience using Verilog and SystemVerilog.
• Strong understanding of control path and data-path digital design concepts with an eye for realizing correct construction solutions.
• Experience with specifying Design Verification (DV) requirements such as test plans, and coverage metrics, and evaluating DV quality to realize robust design quality.
• Knowledge of Lint, CDC, formal equivalence, DFT concepts, and power analysis.
• Experience with developing timing constraints and the ability to carry out logic synthesis and Static timing analysis.
• Good interpersonal, teamwork, and communication skills to logically & effectively drive discussions with teams spread geographically.
• Understanding standard on-chip interfaces such as APB/AHB/AXI/Stream protocols is a strong plus.
• Knowledge of Processor/SoC architecture and/or DSP fundamentals is a strong plus.
• Experience with end-to-end ASIC/SoC product development & productization is very desirable.