DFT Engineer Job in Bangalore at NVIDIA

Nvidia is hiring for the role of DFT Engineer!

Responsibilities of Candidates:

• As a member in our team, you will be responsible for the design and implementation of state-of-the-art designs in test access mechanisms, memory BIST and scan compression.
• Your responsibility will also include verification and silicon bringup of Scan ATPG and other DFT features.
• In addition, you will help develop and deploy DFT methodologies for our next generation products.
• Be apart of innovation to strive improve the quality of DFT methods.
• You will also need to work with multi-functional teams to incorporate DFT features into the chip.
• Occasional travel and also some late hours online meetings involved during critical milestones.

Requirements:

• BSEE or MSEE from reputed institutions or equivalent experience.
• 1+ Years of experience preferably in Design for testability (DFT)
• You should be well versed with static timing Analysis, ECO, ASIC/Logic Design Flow, HDL and Digital logic design.
• Experience in RTL and Gates verification and simulation.
• You need to be familiar with BIST architecture and JTAG/IEEE1149.1/IEEE1500.
• Strong DFT knowledge in Scan ATPG, compression techniques and memory test.
• Strong analytical and problem solving skills.
• Expert coding skills in industry standard scripting languages.
• Extraordinary written and oral communication skills with the curiosity to work on rare challenges.