Design Engineering Architect Job in Bengaluru at Cadence Design Systems

Cadence is hiring for the position of Design Engineering Architect!

Responsibilities of the Candidate:

• Responsible for the design and implementation of high-speed SerDes PHY at the cutting-edge nodes.
• Responsibilities include the architecture of high-speed SerDes IP, design, lint, synthesis, static timing analysis, DFT, and formal verification, at block, core, and chip levels.
• Work closely with Analog design teams to co-develop algorithms, feedback design loops as well and high-speed-critical digital circuits.

Requirements:

• Bachelors in Engineering.
• Proficient in Verilog coding and RTL design, data path designs.
• Knowledge of RTL checks ex-LINT, SDC, CDC.
• Familiar with synthesis flow and timing constraints.
• Experience in writing Verilog testbench and running simulations.
• Desired Protocols knowledge – USB, PCIe, MIPI(DPHY), HDMI/Display.
• Good understanding of the digital design flow.
• Proficient in Verilog coding.
• Proficient in high-speed design, RTL coding, datapath designs, and working at GHz frequencies.