Design Engineer Job in Hyderabad at Silicon Labs

Silicon Labs is hiring for the role of Design Engineer!

Responsibilities of the Candidate:

• Own STA execution for digital blocks or top-level designs
• Develop and validate SDC constraints for RTL-to-GDSII flow
• Analyze setup/hold violations and collaborate with RTL, synthesis, and physical design teams
• Generate and interpret timing reports using industry-standard tools
• Implement timing ECOs to resolve critical path issues
• Contribute to timing methodology improvements and automation
• Perform timing checks for CDC, false paths, and multicycle paths

Requirements:

• 2–4 years of experience in STA for ASIC or SoC development
• Strong understanding of timing fundamentals including PVT variations and clocking schemes
• Proficiency with tools like Synopsys PrimeTime or Cadence Tempus
• Experience in writing and debugging SDC constraints
• Scripting skills in TCL, Perl, or Python
• Exposure to synthesis, floorplanning, and physical design flows
• Strong analytical and communication skills
• B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI, or related fields