Deg Layout Engineer Internship in Hyderabad at Micron

Micron is hiring for the role of Deg Layout Engineer!

Responsibilities of the Candidate: 

• Design and develop critical analog, mixed-signal, custom digital block, and full chip-level integration support
• Perform layout verification like LVS/DRC/Antenna, quality check and support documentation
• Be responsible for on-time delivery of block-level layouts with acceptable quality
• Demonstrate leadership qualities in planning, area/time estimation and execution to meet project schedules/milestones in multiple project environment
• Guide peer team-members in their execution of sub block-level layouts & review critical items
• Contribute to effective project management

Requirements: 

• 2 to 5 years experience in analog/custom layout design in advanced CMOS processes, in various technology nodes (Planar, FinFET)
• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.
• Have hands-on experience in creating layout of critical blocks such as Temperature sensors, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifiers etc.,
• Good understanding of Analog Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc.)
• Understanding layout effects on the circuit such as speed, capacitance, power and area, etc.,
• Ability to understand design constraints and implement high-quality layouts
• Leading Problem-solving skills in physical verification of custom layout
• Multiple Tape out support experience will be an added advantage
• Excellent verbal and written communication skills