ASIC RTL Design Engineer Job in Bangalore at Google

Google Inc. is hiring for the role of ASIC RTL Design Engineer!

Responsibilities of the Candidates:

• Interact closely with the Architecture team and develop microarchitecture and coding to meet quality and Performance Power Area (PPA) for the IP.
• Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
• Participate in synthesis, timing/power closure, and silicon bring-up.
• Participate in test plan and coverage analysis of the IP, sub-system, and chip-level verification.
• Work with multi-disciplined and multi-site teams in RTL design, verification, DFT, physical design, software team, architects.

Requirements:

• Bachelor's/Master's degree in Electrical Engineering or equivalent practical experience.
• 4 years of experience in RTL coding from domains such as interconnect, coherency/non-coherency, or cache.
• Proficiency with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, UPF, and Low Power Optimization/Estimation.
• Understanding of cross-domain involving domain validation, design for testing, physical design, and software.
• Experience in design and multi-power domains with clocking.
• Experience in coding using Verilog or System Verilog.