ASIC Engineer-Design Job in Bangalore at Meta

Meta is hiring for the role of ASIC Engineer!

Responsibilities of the Candidates:

• Micro-architecture development
• RTL development using Verilog, System Verilog, and HLS
• Lint, CDC, synthesis, and power optimization
• Soft and hard IP identification, selection, and integration
• Collaboration with verification and emulation teams in test plan development and debugging
• Collaboration with the implementation team to close the design on timing and power

Requirements:

• 3+ years of silicon development experience
• Experience with Verilog or System Verilog
• Minimum 3 years of expertise in micro-architecture and RTL development for complex control and data path IPs, SoC micro-architecture, design and integration, or implementation and power methodology development
• Currently holds or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience, degree must be completed prior to joining Meta.