ASIC Design For Testability Engineer-Silicon Job in Bengaluru at Google

Google is hiring for the role of ASIC Design For Testability Engineer-Silicon!

Responsibilities of the Candidate:

• Work with a team of DFT engineers, working closely with RTL and Physical Designer Engineers.
• Work on Subsystem level DFT SCAN, Memory Built-In Self Test (MBIST) Architecture with multiple voltage, power domains.
• Write basic to complex scripts to automate the DFT flow.
• Develop tests that can be used for Production in the Automated Test Equipment (ATE) flow.
• Work with members of the DFT team to deliver overall deliverables for 2 or more complex Subsystems in a SoC.

Requirements:

• Bachelor's degree in Computer Science, Electronics or Electrical Engineering, or equivalent practical experience.
• 2 years of experience in design for testability.
• Experience with ATPG, Low Power designs, Built-In Self Test (BIST), Joint Test Action Group (JTAG), Internal Joint Test Action Group (IJTAG) tools and flow.
• Experience with DFT EDA Too Tessent.
• Experience in DFT for a Complex subsystem with multiple physical partitions.
• Experience with IJTAG ICL, PDL terminology, ICL modeling with Siemens Tessent Tool.
• Experience with Spyglass-DFT, and DFT Scan constraints and evaluating DFT STA paths.
• Experience with a scripting laicatnguage such as Perl or Python.
• Understanding of the flows - Design, Verification, DFT and PD Phases in a SOC cycle.